-- OK --
-----------------> BLESK ver.2021-02-27 run on Sun May 26 23:14:42 2024 UTC
-- File 20240526_112539_1224.dat, 1  packets found.
APID:
      1224 (INIT) in 1 packets (all packets)
Mode:
      1 (EBEW-SRSL) in 1 packets (all packets)
Total number of packets: 
      1 in 1 packets (all packets)
Packet No from 1 to 1
Hz and MHz counters from 0.000000 to 0.000000
-each separately from 0s to 0s and from 0us to 0us.
MIU packet time from 2024-05-26T11:25:42.000.000.000 to 2024-05-26T11:25:42.000.000.000
MIU orbit number: 
      60000 in 1 packets (all packets)
MIU orbit information / directon: 
      0 (DOWN) in 1 packets (all packets)
MIU orbit information / number of events: 
      0 in 1 packets (all packets)
Waveform overflows in 306us: 
      0 (none) in 1 packets (all packets)
Instrument anomalies: 
      0 (OK) in 1 packets (all packets)
FPGA configuration version: 
      211 in 1 packets (all packets)
10 MHz counter at the last 1Hz pulse from 0.0000000 to 0.0000000
Temperature FPGA: 
      00 -> 55.0 degC in 1 packets (all packets)
Temperature XO: 
      00 -> -273.1 degC in 1 packets (all packets)
Temperature ant 3: 
      00 -> 115.9 degC in 1 packets (all packets)
Temperature ant 4: 
      00 -> 115.9 degC in 1 packets (all packets)
Number of external events: 
      0 in 1 packets (all packets)
Number of generated alerts: 
      0 in 1 packets (all packets)
Survey memory error: 
      0 in 1 packets (all packets)
Event memory error: 
      0 in 1 packets (all packets)
Configuration error: 
      0 in 1 packets (all packets)
SDRAM CRC error: 
      0 in 1 packets (all packets)
Radio gain: 
      0 in 1 packets (all packets)
Radio bandwidth: 
      0 in 1 packets (all packets)
Digital gain: 
      0 in 1 packets (all packets)
Analog gain: 
      12 in 1 packets (all packets)

Configuration from the INI packet written to 20240526_112539_1224.asc

Configuration check: mode validity (other than 0, 14 or 15): OK
Configuration check: completeness of CONFHFA (19 bytes)    : OK
Configuration check: completeness of HFPE/RW (19+120 bytes): OK
Configuration check: number of received CONFHFA bytes      : 19
Configuration check: number of HFPE/RW intervals (max. 20) : 20

Stack1 memory test: writing 0: OK    writing 1: OK
Stack2 memory test: writing 0: OK    writing 1: OK

SDRAM memory test: OK
Addr  01A9BDB0 017D6360 03C3D2D0 00223BB0 00332660 03155AA0 009FF7F0 00D00C00 00B80A00 00E40F00 00960880
      00960880 00DD0CC0 00B38AA0 02EA4FF0 039F6800 01286E00 00DE2C80 00B13AC0 00E9A7A0 029D7470 03D3CE40
      03D3CE40 023A2960 01273DD0 03B4A330 026EF2A0 01598BF0 00FAA700 0043FA40 00620760 025304D0 017A86B0
      017A86B0 01C7C5E0 03242710 00B63490 02ED2ED0 019BB9B0 01566560 03FEABE0 0200FF00 03008080 0280C0C0
      0280C0C0 03C0A0A0 0020F0F0 00308880 0028CCC0 003CAAA0 0222FFF0 03338000 01552000 00FFD800 00803400
      00803400 00C02E00 00A03900 00F02580 00883740 00CC2CE0 02AA3A90 01FF27D0 0300B430 03407710 02702640
      02702640 03483560 00EC2FD0 029A3830 03D72420 003CB630 0022ED20 02339BB0 032A5660 00BF7D50 017061F0
      017061F0 00E42880 00963CC0 00DD22A0 02B3B3F0 03EA6A00 021F5F00 0310F080 029888C0 03D4CCA0 003EAAF0
      003EAAF0 0010FFC0 020C4010 010A6010 038F5010 0048F810 026C8410 015AC610 03F7A510 000C7790 020A4C50
      020A4C50 010F6A70 00C46FA0
     
