-- OK --
-----------------> BLESK ver.2021-02-27 run on Wed Apr 24 23:36:40 2024 UTC
-- File 20240422_042001_1224.dat, 1  packets found.
APID:
      1224 (INIT) in 1 packets (all packets)
Mode:
      1 (EBEW-SRSL) in 1 packets (all packets)
Total number of packets: 
      1 in 1 packets (all packets)
Packet No from 1 to 1
Hz and MHz counters from 0.000000 to 0.000000
-each separately from 0s to 0s and from 0us to 0us.
MIU packet time from 2024-04-22T04:20:04.000.000.000 to 2024-04-22T04:20:04.000.000.000
MIU orbit number: 
      60000 in 1 packets (all packets)
MIU orbit information / directon: 
      0 (DOWN) in 1 packets (all packets)
MIU orbit information / number of events: 
      0 in 1 packets (all packets)
Waveform overflows in 306us: 
      0 (none) in 1 packets (all packets)
Instrument anomalies: 
      0 (OK) in 1 packets (all packets)
FPGA configuration version: 
      211 in 1 packets (all packets)
10 MHz counter at the last 1Hz pulse from 0.0000000 to 0.0000000
Temperature FPGA: 
      00 -> 55.0 degC in 1 packets (all packets)
Temperature XO: 
      00 -> -273.1 degC in 1 packets (all packets)
Temperature ant 3: 
      00 -> 115.9 degC in 1 packets (all packets)
Temperature ant 4: 
      00 -> 115.9 degC in 1 packets (all packets)
Number of external events: 
      0 in 1 packets (all packets)
Number of generated alerts: 
      0 in 1 packets (all packets)
Survey memory error: 
      0 in 1 packets (all packets)
Event memory error: 
      0 in 1 packets (all packets)
Configuration error: 
      0 in 1 packets (all packets)
SDRAM CRC error: 
      0 in 1 packets (all packets)
Radio gain: 
      0 in 1 packets (all packets)
Radio bandwidth: 
      0 in 1 packets (all packets)
Digital gain: 
      0 in 1 packets (all packets)
Analog gain: 
      12 in 1 packets (all packets)

Configuration from the INI packet written to 20240422_042001_1224.asc

Configuration check: mode validity (other than 0, 14 or 15): OK
Configuration check: completeness of CONFHFA (19 bytes)    : OK
Configuration check: completeness of HFPE/RW (19+120 bytes): OK
Configuration check: number of received CONFHFA bytes      : 19
Configuration check: number of HFPE/RW intervals (max. 20) : 20

Stack1 memory test: writing 0: OK    writing 1: OK
Stack2 memory test: writing 0: OK    writing 1: OK

SDRAM memory test: OK
Addr  017BD2D0 03C63BB0 02252660 0137B550 03AC6FF0 027A5800 03477400 01726700 00E5AA40 024BBFB0 03B73030
      03B73030 03365410 00AD7E10 02FBC110 01862190 03453150 00E7A9F0 00947D00 00DE4380 00B16240 00E9D360
      00E9D360 034E9D60 0274E9E0 014E9D10 03E9D390 001D3A50 0213A770 031A74C0 02974EA0 01DCE9F0 01329D00
      01329D00 01ABD380 00BF1D20 017049D0 03C86D30 022C5BA0 013A7670 01A74D40 0174EBE0 03CE9E10 0029D110
      0029D110 023D3990 0123A550 01D93BF0 009AD300 00D7BA80 00BC67C0 00E25420 02937E30 03DAC120 0037A1B0
      0037A1B0 002C7160 023A49D0 01276D30 02DA6DD0 00DBAD90 02B67B50 01ED46F0 011BE580 01961740 015D1CE0
      015D1CE0 03F39290 000A5BD0 020F7630 0308CD20 004655D0 0132BF90 03ABE050 007E1070 00411840 00619460
      00619460 02515E50 0179F170 01C509C0 01278D20 03B44BB0 03373730 03565650 00FD7D70 0083C3C0 00C22220
      00C22220 02A33330 03F2AAA0 000BFFF0 000E0000 00090000 000D8000 0005A000 0003B800 00026400 00035600
      00035600 0002FD00 00038380
     
