-- OK --
-----------------> BLESK ver.2021-02-27 run on Thu May 23 23:09:05 2024 UTC
-- File 20240523_073748_1224.dat, 1  packets found.
APID:
      1224 (INIT) in 1 packets (all packets)
Mode:
      1 (EBEW-SRSL) in 1 packets (all packets)
Total number of packets: 
      1 in 1 packets (all packets)
Packet No from 1 to 1
Hz and MHz counters from 0.000000 to 0.000000
-each separately from 0s to 0s and from 0us to 0us.
MIU packet time from 2024-05-23T07:37:51.000.000.000 to 2024-05-23T07:37:51.000.000.000
MIU orbit number: 
      60000 in 1 packets (all packets)
MIU orbit information / directon: 
      0 (DOWN) in 1 packets (all packets)
MIU orbit information / number of events: 
      0 in 1 packets (all packets)
Waveform overflows in 306us: 
      0 (none) in 1 packets (all packets)
Instrument anomalies: 
      0 (OK) in 1 packets (all packets)
FPGA configuration version: 
      211 in 1 packets (all packets)
10 MHz counter at the last 1Hz pulse from 0.0000000 to 0.0000000
Temperature FPGA: 
      00 -> 55.0 degC in 1 packets (all packets)
Temperature XO: 
      00 -> -273.1 degC in 1 packets (all packets)
Temperature ant 3: 
      00 -> 115.9 degC in 1 packets (all packets)
Temperature ant 4: 
      00 -> 115.9 degC in 1 packets (all packets)
Number of external events: 
      0 in 1 packets (all packets)
Number of generated alerts: 
      0 in 1 packets (all packets)
Survey memory error: 
      0 in 1 packets (all packets)
Event memory error: 
      0 in 1 packets (all packets)
Configuration error: 
      0 in 1 packets (all packets)
SDRAM CRC error: 
      0 in 1 packets (all packets)
Radio gain: 
      0 in 1 packets (all packets)
Radio bandwidth: 
      0 in 1 packets (all packets)
Digital gain: 
      0 in 1 packets (all packets)
Analog gain: 
      12 in 1 packets (all packets)

Configuration from the INI packet written to 20240523_073748_1224.asc

Configuration check: mode validity (other than 0, 14 or 15): OK
Configuration check: completeness of CONFHFA (19 bytes)    : OK
Configuration check: completeness of HFPE/RW (19+120 bytes): OK
Configuration check: number of received CONFHFA bytes      : 19
Configuration check: number of HFPE/RW intervals (max. 20) : 20

Stack1 memory test: writing 0: OK    writing 1: OK
Stack2 memory test: writing 0: OK    writing 1: OK

SDRAM memory test: OK
Addr  028D3330 03CBAAA0 002E7FF0 00394000 0025E000 00371000 002C9800 003AD400 0013DF00 000D1840 0205CA30
      0205CA30 03072F20 0084B8B0 00C6E4E0 02A59690 01F75DD0 030CF330 028A8AA0 01CFCFF0 01282800 00DE1E00
      00DE1E00 00588880 0074CCC0 004EAAA0 0269FFF0 035D0000 02F38000 038A4000 024F6000 0368D000 02DCB800
      02DCB800 01D97200 009AE580 00D79740 00BC5CE0 02E27290 01934BD0 035AEE30 02F79920 018C55B0 014A7F60
      014A7F60 03EF40D0 000C7050 01052430 0187B620 03446D30 02E65BA0 01957670 015FCD40 01F02BE0 03083E10
      03083E10 008C2110 02CA3190 02D794A0 00DE2F70 00B138C0 00E9A4A0 029D76F0 03D3CD80 023A2B40 03273EE0
      03273EE0 00B4A190 02EEF150 019989F0 00AAA680 007FFAE0 02400790 01600450 03D00670 02380540 032407E0
      032407E0 00B60410 02ED0610 019B8510 03564790 027EB220 00A0F590 02F08F50 0188C8F0 014CAC80 01EAFAC0
      01EAFAC0 011F87A0 03904470 02586640 03745560 00CE7FD0 0154A010 03FF7800 0200C400 0300A600 0280F500
      0280F500 03C08F80 0220C840
     
