-- OK --
-----------------> BLESK ver.2021-02-27 run on Sat May 18 23:25:31 2024 UTC
-- File 20240518_195623_1224.dat, 1  packets found.
APID:
      1224 (INIT) in 1 packets (all packets)
Mode:
      1 (EBEW-SRSL) in 1 packets (all packets)
Total number of packets: 
      1 in 1 packets (all packets)
Packet No from 1 to 1
Hz and MHz counters from 0.000000 to 0.000000
-each separately from 0s to 0s and from 0us to 0us.
MIU packet time from 2024-05-18T19:56:26.000.000.000 to 2024-05-18T19:56:26.000.000.000
MIU orbit number: 
      60000 in 1 packets (all packets)
MIU orbit information / directon: 
      0 (DOWN) in 1 packets (all packets)
MIU orbit information / number of events: 
      0 in 1 packets (all packets)
Waveform overflows in 306us: 
      0 (none) in 1 packets (all packets)
Instrument anomalies: 
      0 (OK) in 1 packets (all packets)
FPGA configuration version: 
      211 in 1 packets (all packets)
10 MHz counter at the last 1Hz pulse from 0.0000000 to 0.0000000
Temperature FPGA: 
      00 -> 55.0 degC in 1 packets (all packets)
Temperature XO: 
      00 -> -273.1 degC in 1 packets (all packets)
Temperature ant 3: 
      00 -> 115.9 degC in 1 packets (all packets)
Temperature ant 4: 
      00 -> 115.9 degC in 1 packets (all packets)
Number of external events: 
      0 in 1 packets (all packets)
Number of generated alerts: 
      0 in 1 packets (all packets)
Survey memory error: 
      0 in 1 packets (all packets)
Event memory error: 
      0 in 1 packets (all packets)
Configuration error: 
      0 in 1 packets (all packets)
SDRAM CRC error: 
      0 in 1 packets (all packets)
Radio gain: 
      0 in 1 packets (all packets)
Radio bandwidth: 
      0 in 1 packets (all packets)
Digital gain: 
      0 in 1 packets (all packets)
Analog gain: 
      12 in 1 packets (all packets)

Configuration from the INI packet written to 20240518_195623_1224.asc

Configuration check: mode validity (other than 0, 14 or 15): OK
Configuration check: completeness of CONFHFA (19 bytes)    : OK
Configuration check: completeness of HFPE/RW (19+120 bytes): OK
Configuration check: number of received CONFHFA bytes      : 19
Configuration check: number of HFPE/RW intervals (max. 20) : 20

Stack1 memory test: writing 0: OK    writing 1: OK
Stack2 memory test: writing 0: OK    writing 1: OK

SDRAM memory test: OK
Addr  014DEDD0 03EB1B30 021E96A0 0111DDF0 00CC9980 00556AA0 013FEFF0 01A01800 01701400 01C81E00 012C1100
      012C1100 01BA1980 01671540 01D49FE0 033ED010 00A1B810 0378B200 01627580 01D34F40 013AE8E0 03A79C90
      03A79C90 007452D0 024E7BB0 03694660 00DDE550 02B317F0 03EA9C00 010FE900 00C40EC0 00A609A0 02F50D70
      02F50D70 038F8BC0 02484E20 016C6930 01DA5DA0 03377370 02ACCAC0 03FAAFA0 0003FC30 02010110 01018190
      01018190 03814150 0041E1F0 00611100 00519980 00795540 0045FFE0 02670010 01548010 03FF6000 01006800
      01006800 01805C00 01407200 01E04B00 01106E80 019859C0 01547520 03FE4FB0 02016860 0101DC50 01C09930
      01C09930 02906AD0 01D85FB0 01347060 03AE4850 00796C70 0045DA40 00673760 0254ACD0 017EFAB0 01C187E0
      01C187E0 0390A200 012C7980 01BA4540 016767E0 03D4D410 003EBE10 0221E110 01311190 03A99950 007D55F0
      007D55F0 0043FF00 00310040 0214C030 031EA020 0091F030 00D90820 02B58C30 03EF4A20 0018EF30 001498A0
      001498A0 021ED4F0 0311BE80
     
