-- OK --
-----------------> BLESK ver.2021-02-27 run on Sun Jan 28 20:54:21 2024 UTC
-- File 20231018_114954_1224.dat, 1  packets found.
APID:
      1224 (INIT) in 1 packets (all packets)
Mode:
      1 (EBEW-SRSL) in 1 packets (all packets)
Total number of packets: 
      1 in 1 packets (all packets)
Packet No from 1 to 1
Hz and MHz counters from 0.000000 to 0.000000
-each separately from 0s to 0s and from 0us to 0us.
MIU packet time from 2023-10-18T11:49:57.000.000.000 to 2023-10-18T11:49:57.000.000.000
MIU orbit number: 
      60000 in 1 packets (all packets)
MIU orbit information / directon: 
      0 (DOWN) in 1 packets (all packets)
MIU orbit information / number of events: 
      0 in 1 packets (all packets)
Waveform overflows in 306us: 
      0 (none) in 1 packets (all packets)
Instrument anomalies: 
      0 (OK) in 1 packets (all packets)
FPGA configuration version: 
      211 in 1 packets (all packets)
10 MHz counter at the last 1Hz pulse from 0.0000000 to 0.0000000
Temperature FPGA: 
      00 -> 55.0 degC in 1 packets (all packets)
Temperature XO: 
      00 -> -273.1 degC in 1 packets (all packets)
Temperature ant 3: 
      00 -> 115.9 degC in 1 packets (all packets)
Temperature ant 4: 
      00 -> 115.9 degC in 1 packets (all packets)
Number of external events: 
      0 in 1 packets (all packets)
Number of generated alerts: 
      0 in 1 packets (all packets)
Survey memory error: 
      0 in 1 packets (all packets)
Event memory error: 
      0 in 1 packets (all packets)
Configuration error: 
      0 in 1 packets (all packets)
SDRAM CRC error: 
      0 in 1 packets (all packets)
Radio gain: 
      0 in 1 packets (all packets)
Radio bandwidth: 
      0 in 1 packets (all packets)
Digital gain: 
      0 in 1 packets (all packets)
Analog gain: 
      12 in 1 packets (all packets)

Configuration from the INI packet written to 20231018_114954_1224.asc

Configuration check: mode validity (other than 0, 14 or 15): OK
Configuration check: completeness of CONFHFA (19 bytes)    : OK
Configuration check: completeness of HFPE/RW (19+120 bytes): OK
Configuration check: number of received CONFHFA bytes      : 19
Configuration check: number of HFPE/RW intervals (max. 20) : 20

Stack1 memory test: writing 0: OK    writing 1: OK
Stack2 memory test: writing 0: OK    writing 1: OK

SDRAM memory test: OK
Addr  0030E0A0 022890F0 033CD880 02A2B4C0 03F3EEA0 000A19F0 000F1500 00089F80 000CD040 000AB860 020FE450
      020FE450 01081670 018C1D40 014A13E0 03EF1A10 020C4B80 030A6E40 028F5960 01C8F5D0 032C8F30 02BAC8A0
      02BAC8A0 01E7ACF0 01147A80 019E47C0 01516420 01FCEB10 03814F40 0241E8E0 01611C90 03D192D0 00395BB0
      00395BB0 0025F660 02370D50 012C8BF0 01BACE00 0167A900 00EA3EC0 024F90D0 016858B0 01DC74E0 03324E90
      03324E90 00AB69D0 02FEDD30 0381B3A0 00416A70 0061DF40 005130E0 033CD440 03515F30 02F9F0A0 018508F0
      018508F0 01478C80 01E44AC0 01166FA0 039D5870 0253F440 037A0E60 00C70950 015246F0 00FDB2C0 00836BA0
      00836BA0 02C2DE70 03A3B140 027269E0 014B5D10 03EEF390 00198A50 02154F70 031FE8C0 03480E50 007604B0
      007604B0 004D06E0 026B8590 015E4750 03F164F0 0209D680 030D3DC0 028BA320 01CE72B0 01294BE0 03DEF700
      03DEF700 0118C640 0194A560 035EF7D0 00F18C30 00894A20 02CDEF30 03AB18A0 007E94F0 0041DE80 006131C0
      006131C0 0228D490 029E5F60
     
